Gekko 2001 年 · GameCube IBMNintendo 基本参数 主频486 MHz 核心架构750CXe 核心（定制增强） 核心 Gekko 微架构简图 32-Bit Address · 64-Bit Data 60x Bus Data 系统总线与片内 L2 System Bus & On-Chip L2 指令单元与 MMU Instruction Unit & MMUs 保留站 Reservation Stations 执行单元 Execution Units 寄存器堆 Register Files 完成单元 Completion Unit 60x Bus Interface Unit (Instr Fetch · Castout · Load Qs · Write Gather Pipe) On-Chip L2 Controller (256KB, 2-Way) On-Chip L2 Cache 32KB L1 I-Cache (8-Way SA) 32KB L1 D-Cache (8-Way SA · MEI · Lockable) I-MMU (ITLB 128-E) D-MMU (DTLB 128-E) Fetcher BPU (BTIC 64-E · BHT 512-E) Instr Queue (6-Word) Dispatch Unit (2/cyc) RS RS RS RS RS (2-E) IU1 (+ × ÷) IU2 (+ Shift/Rotate) SRU (CR · GQRs) FPU (Paired Single) LSU (+EA · DMA) GPR File (32 + 6 Renames) FPR File (32 + 6 Renames · Paired Single) Completion Unit (6-Entry ROB) Store Q 播放 该型号微架构图建设中 技术特点 Paired Single 配对单精度片内 256KB L2Write Gather Pipe 相关文章 暂无关联文章
Xenon 2005 年 · Xbox 360 IBMMicrosoft 基本参数 主频3.2 GHz 核心架构三核 PPE 架构 缓存1MB 共享 L2 微架构简图 微架构简图占位 技术特点 VMX128 SIMD 相关文章 暂无关联文章
Cell BE 2006 年 · PlayStation 3 IBMSonyToshiba 基本参数 主频3.2 GHz 核心架构1×64位 PPE 主核 + 8×SPE 协处理器 缓存512KB L2 核心 PPE 64 位双线程主核 SPE SIMD 协处理核 ×8 微架构简图 Decoupled · Out-of-Order Issue D-Cache Data 2-Way SMT · 23-Stage Pipeline 系统总线与 L2 System Bus & L2 Cache 指令单元与 L1 缓存 Instruction Unit & L1 Caches 解码与发射（按序·双发）Decode & Issue 执行单元 Execution Units 寄存器堆（每线程 A/B）Register Files 完成 Completion / Flush EIB Interface / BIU (Coherent Ring · 96 B/cyc Peak) L2 Cache (512KB) (Unified · RMT Managed) 32KB L1 I-Cache (2-Way SA) 32KB L1 D-Cache (4-Way SA · Non-Blocking) Branch Prediction (4KB BHT · 6-bit GHist) Fetch Control (Threads A & B · 4 Instr/cyc/Thr) Instruction Buffer Decode Dependency Check Issue Logic (In-Order · Dual) VSU Issue Queue (Decoupled) BRU (Branch) FXU (Int · 2-cyc) LSU (Load/Store · Non-Blk) VMX (Vector) (128-bit · Simple/Cplx/Perm/FP) FPU (Scalar) (Double Precision · 10-Stage) GPR File (32 × 64-bit) (Per Thread A / B) VRF File (32 × 128-bit) (Per Thread A / B) FPR File (32 × 64-bit) (Per Thread A / B) Completion / Flush Unit 播放 16 B Load/Store 128 B DMA 128 B Instr Prefetch (LS idle) Element Interconnect Bus (EIB) 取指与分发 Instruction Fetch & Issue 执行流水线 Execution Pipelines 前递与统一寄存器 Forwarding & Register File 局部存储 Local Store 内存流控制器 Memory Flow Controller Branch Handling No HW Predictor · SMBTB (SW) Instruction Fetch & Issue ILB 3.5-Line · Dual-Issue · In-Order Even Pipeline Simple Fixed (2-cyc) Shift Operations Single Precision FP (6-Stage · Truncate) FP to Integer Byte Operations Odd Pipeline Permute Local Store Access (16 B) Channel (rdch / wrch) Branch Result Forwarding Macro (6 Read Ports · Bypass) Unified Vector Register File (128 × 128-bit · 6 Read / 2 Write) Local Store — 256KB Single-Port SRAM No Hardware Cache · Deterministic 6-Cycle Latency Memory Flow Controller (MFC) — Async · up to 16 DMA in-flight DMA Queue SPU + Proxy DMA Engine List (2048) Scatter/Gather MMU & RMT 64-bit EA · SLB/TLB Atomic Facility getllar / putllc 播放 该型号微架构图建设中 技术特点 双线程 SMT PPE8× SIMD SPE256KB Local StoreEIB 环形总线 相关文章 暂无关联文章